FIGS. 6(a) and 6(b) illustrate the structure of a conventional MOS mask ROM disclosed in Japanese Unexamined Patent Publication No. Sho 61-288464. The MOS mask ROM disclosed in the publication is a flat-cell MOS mask ROM in which a diffusion layer formed by ion implantation is formed on an isolation region to form a flat surface. Thus, the flat-cell mask ROM is different than a mask ROM in which an isolation region is formed by selective oxidization by using a LOCOS process. FIG. 6(a) is a top view of the conventional MOS mask ROM, and FIG. 6(b) shows a cross sectional view along line B-B' in FIG. 6(a).
As shown in the figures, the MOS mask ROM comprises a P silicon substrate 100, and linear N.sup.+ buried regions 101 and 102 are alternatively formed in parallel in one direction on the substrate 1. The N.sup.+ buried region 101 forms a source region for a plurality of memory transistors (e.g. transistors "a" and "b") and corresponds to a ground line of the mask ROM. The N.sup.+ buried region 102 forms a drain region for the transistors "a" and "b" and corresponds to a bit line of the mask ROM. Also, a gate oxide film 110 is formed over the substrate 100 and the N.sup.+ buried regions 101 and 102, and a plurality of a parallel word lines 103 made of polysilicon are formed on the gate oxide film 110. Also, the word lines 103 are formed perpendicularly to the linear N.sup.+ buried regions 101 and 102 and serve as the gate electrodes of a plurality of memory transistors (e.g. transistors "a" and "c") in the mask ROM.
In addition, as shown in FIG. 6(a) P.sup.+ isolation regions 200 (illustrated as crosshatched squares) are ion-implanted via a self-alignment process based on the N.sup.+ buried regions 101 and 102 and the word lines 103. In other words, the N.sup.+ buried regions 101 and 102 are very highly doped, and thus, the implanting of ions to form the P.sup.+ isolation regions 200 does not change the N.sup.+ buried regions 101 and 102 into P.sup.+ regions. Therefore, the word lines 103 can be used as a mask for the regions other than the N.sup.+ buried regions 101 and 102, and a separate mask does not need to be formed over the regions 101 and 102 when the P.sup.+ isolation regions 200 are formed. Each of the isolation regions 200 serves as an isolation region between adjacent memory transistors formed by adjacent word lines 103. For example, the transistor "a" and the transistor "b" are located on adjacent word lines 103 and are separated by the isolation region 200a. Also, a region which is located between the N.sup.+ buried region 101 and the N.sup.+ buried region 102 and is located directly below the word line 103 is a channel region 201. Thus, each of the transistors in ROM have a channel region 201.
In the conventional MOS mask ROM mention above, the data stored in the ROM (i.e. a ROM code) is formed by selectively doping certain memory transistors with boron. Specifically, a resist pattern is formed via a photolithography process over the MOS mask ROM and boron is doped into selected transistors while using the resist as a mask. (Such a process is referred to as a "code boron doping process"). Since the threshold voltage V.sub.T of a boron-doped memory transistor increases and the threshold voltage V.sub.T of an undoped transistor remains the same, data can be read from the ROM based on the difference between the thresholds voltages V.sub.T of the transistor. For example, a transistor having a high threshold voltage V.sub.T will not turn ON when a voltage V.sub.READ (having a voltage lower than the high threshold voltage V.sub.T) is applied to its gate electrode (i.e. the word line 103). On the other hand, a transistor having a normal threshold voltage V.sub.T will turn on when the voltage V.sub.READ is applied to the gate electrode (i.e. the word line 103). The ROM may consider the transistors that do not turn on to output a logic "1" and may consider the transistors that do turn on to output a logic "0".
Generally, the mask ROM also has bank selector lines in addition to the word lines 103. Therefore, in addition to doping transistors with boron to create the ROM code, predetermined cells formed by the bank selector lines need to be doped with boron to create channel stops in the predetermined cells in order to sever an undesired current path when data is read from the ROM. (The process of doping boron in predetermined cells formed by the bank selector lines is referred to as a "channel stop boron doping process").
The conventional MOS mask ROM suffers from several disadvantages. For example, as shown in FIG. 7(a), the design of the mask ROM requires an interlayer film 104 having a thickness of 3000 to 5000 angstrom to be formed over the word lines and/or bank selector lines 103. Then, in order to perform the code boron doping process and/or channel stop boron doping process, a resist 106 is formed over the interlayer film 104, and the resist 106 has openings which correspond to the portions of the ROM which are to be ion implanted with boron during the doping processes. Then, boron is doped into the transistor cells via an ion implantation process while using the resist 106 as a mask. Since the boron must travel through the interlayer film 104, the implantation process is conducted with an implantation energy of about 200 to 350 KeV to form a boron implantation region 105. Since such a large amount of ion implantation energy is used to implant the boron, the boron implantation region 105 becomes relatively large and seeps into a portion below an adjacent word line (or bank selector line) 103. (See FIG. 7(a)).
In contrast, FIG. 7(b) illustrates an earlier process in which boron ions can be implanted to form a boron doped region 105A of a semiconductor device which does not require the use of an interlayer film during the doping process. Since the boron does not have to travel through an interlayer film, the boron can be implanted with an ion implantation energy of only 100 to 150 KeV using a photoresist 106A. Thus, as shown in the figure, the boron doped region 105A does not seep into a region below an adjacent word line (or bank selector line) 103A. However, after the boron is implanted, an interlayer layer must be formed over the doped region 105A and the word line (or bank selector line) 103A. Therefore, the customization of the ROM for a particular customer must be done before the interlayer layer is formed. Such processes inhibit the speed with which the ROMs can be mass produced.
In the conventional MOS mask ROM, when the boron doped region 105 seeps into the portion below the adjacent word line 103, the threshold voltage V.sub.T of a memory cell formed by the adjacent word line 103 increases, and thus, the speed at which data can be read from the adjacent cell increases. The above problem is not limited to a flat-cell ROM. For example, in a MOS mask ROM in which an isolation region is formed by an isolation diffusion process, a similar problem occurs because the implantation of ions to form the ROM code is performed by doping ions through an interlayer film. Thus, the doped ion region becomes large and seeps into adjacent regions corresponding to adjacent memory cells for the reasons presented above in conjunction with FIG. 7(a).